1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device in which a memory cell and a write/read circuit are driven by different power supply voltages, and in which the power supply voltage for the write/read circuit is shut off during standby to reduce a standby current.
2. Description of the Background Art
Conventionally, a reduction in standby current has been promoted in an SRAM (Static Random Access Memory). In some SRAMs, a power supply voltage SVDD for a memory cell and a power supply voltage VDD for a peripheral circuit are separately supplied, and power supply voltage VDD for the peripheral circuit is shut off during standby to reduce a standby current. Note that power supply voltage SVDD for the memory cell is not shut off even during standby for retaining stored data.
Furthermore, in other SRAMs, a source voltage of a driver transistor for a memory cell is increased to a voltage (0.3 V) slightly higher than a ground voltage VSS during standby, to promote reduction in subthreshold leakage current in the memory cell, while retaining stored data (see ISSCC 2004/SESSION 27/SRAM/27.2 “A 300 MFz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor”, Masanao Yamaoka et al.).
However, a standby current has not sufficiently been reduced in the conventional SRAM.